CVE detail
CVE-2020-24512 — CVE-2020-24512
Published 2021-06-09 · Modified 2026-06-17 · Vendor intel · Product microcode · Source nvd
LOW
severity
CVSS-derived band
0.0038
EPSS probability
exploitation probability, 30d
31.0%
EPSS percentile
percentile vs all CVEs
NOT LISTED
CISA KEV
known exploited catalog
Description
Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
Remediation
No vendor-published fix data in our corpus for this CVE. Check the references below or the vendor's PSIRT / security advisories page.
References